Read-only memory (ROM) has been widely used in computers and electronic devices. In standard ROM (also known as mask ROM), data is physically encoded in the circuit, thus it is usually programmed once during fabrication e.g. at the foundry.
FIG. 1a shows a schematic circuit diagram illustrating example standard ROM cells. FIG. 1b shows a schematic circuit diagram illustrating conventional connections to a sense amplifier. A conventional ROM cell uses a single transistor for storing an information bit by having a single data line discharging or non-discharging depending on the data on accessing the ROM cell. Typically, as standard ROM cells do not include complementary bit lines, the sense amplifier has one end connected to a bit line (BL) and another end connected to a reference node with fixed voltage VDD (equal to the pre-charge level of the BL). The sense amplifier is set unbalanced in favour of the reference node to differentiate between a “0” data (Rd0) and a “1” data (Rd1). The unbalance in the differential sense amplifier may be created through various means. For example, in the sense amplifier shown in FIG. 1b the unbalance is created by the sizes of Transistors M1 and M2, e.g. Transistor M2 has a greater width than Transistor M1 [M2(W)>M1(W)].
Thus, in the conventional ROM cell, the single data line needs to discharge more to overcome the offset of the unbalanced sense amplifier for Rd0, thus compromising the ability to achieve a high speed. Also, in case of a supply bump or dip, the effect directly influences the reference node, but not the BL as at the time of evaluation its pre-charge is Off (the BL is not connected to the supply). This can lead to a wrong decision from the sense amplifier. Further, the unbalanced sense amplifier has a large a variation of offset with respect to voltage.
There have been some attempts at overcoming the above problems. One proposed approach discloses a complementary ROM cell with two transistors per bit. In this approach, the two transistors storing complementary logic states form a memory cell and store a data bit, as shown in FIG. 2a. One transistor has a source terminal connected to a ground terminal while the other transistor has a source terminal left unconnected, representing e.g. a “0” data. This arrangement is reversed for a “1” data. The drain terminal of each of the two transistors is connected to a corresponding one of a differential bit-line pair which provides a differential signal representing the stored data bit to a sense amplifier.
However, in this approach, the ROM core area is about twice the area than that of the conventional ROM cell, as determined by active to active distance of the device. Also, the width of the single transistor is still the same with 100% area overhead, thus there is substantially no gain in the BL discharge rate.
Another proposed approach discloses a ROM cell having localized reference bit lines, as shown in FIG. 2b. In this approach, a reference bit line refBL is input to one side of a differential sense amplifier while a selected data bit line, BL0 or BL1, is input to the other side. The reference bit line refBL is pre-charged and includes two columns 202, 204; the first column 202 includes devices, e.g. 206, that are matched to memory cell devices wherein a device of the selected word line, e.g. WL0, WL1, will be selected to discharge the reference bit line refBL. The second column 204 includes a recessed oxide device, e.g. 208, corresponding to each memory cell in the column.
As the capacitance of the reference line in this approach is about twice that of a conventional bit line, the discharge rate using such reference line is about half of that using the normal bit line. Thus, the effective differential current is only about half of the actual current. In addition, in the Rd0 case, the two transistors are both ON using this approach. Due to statistical variation, their difference is typically very small, thus becoming a constraint for high-speed operation.
A need therefore exists to provide a complementary ROM cell and method for manufacturing the same that seek to address at least one of the above problems.